Danm.Schematic (Danm v0.2.0)

A schematic is a design entity composed inside Danm.

Most of the functions in this module are supposed to be called from withing your own build/1 function, and are builder functions. a builder function is a function that take an input schematic as the first argument, and output a new schematic. What you have in your own build/1 function should be mostly a big chain of builder functions, chanined by the pipe operator.

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Functions

add a sub module instance. optional arguments

assign an expression to a wire optional arguments

make some one bit wire that represent the state of a FSM

connect all pins in the design by name if possible Only connect conservatively, so all connected pins are of the same width, with 0 or 1 driver

expose every wire that is either not loaded or driven.

helper macro to maintain flow of the pipe operator

bundle expressions to a wire with given op optional arguments

pick one choice out of n choices based on first none zero condition. the list is a list of {condition, choice} tuple optional arguments

connect pins together as a wire pins are specified as a list of "inst/port". optional arguments

create an input port optional arguments

pick one choice out of 2^n choices based on condition value optional arguments

define an assertion. If the given expr evalue to verilog reue value the simulation will die

expose the wire as a port. width and direction are automatically figured out

define a finite state machine, from a list of: {state, transitions} where state is a atom. transition is a list of: {condition, next_state}

Invoke the func with s. This is used to keep the pipe flowing

This is Enum.reduce with first 2 argument switched, to keep the pipe flowing

sink one wire or a list of wires, so they have a fake load and not to be auto-exposed

pick one choice out of n choices based on subject matching condition. the list is a list of {condition, choice} tuple optional arguments

Link to this section Functions

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add(s, name, options \\ [])

add a sub module instance. optional arguments:

  • :as, instance name. if nil, a name as u_MODULE_NAME is used
  • :parameters, a map of additional parameters to set before elaborate
  • :connections, a map of port to wire name for connection
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assign(s, str, options \\ [])

assign an expression to a wire optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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assign_fsm(s, fsm_name, options \\ [])

make some one bit wire that represent the state of a FSM

options are a list of: state: name.

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auto_connect(s)

connect all pins in the design by name if possible Only connect conservatively, so all connected pins are of the same width, with 0 or 1 driver

expose every wire that is either not loaded or driven.

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bind_to(value, name)

(macro)

helper macro to maintain flow of the pipe operator

a |> bind_to(b) is just a fancy way to say b = a

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bundle(s, strs, options \\ [])

bundle expressions to a wire with given op optional arguments:

  • :as, name of the wire. required
  • :with, one of (:comma, :and, :or, :xor). default to :comma
  • :flop_by, clock name of the flop
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condition(s, list, options \\ [])

pick one choice out of n choices based on first none zero condition. the list is a list of {condition, choice} tuple optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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connect(s, conns, options \\ [])

connect pins together as a wire pins are specified as a list of "inst/port". optional arguments

  • :as, wire name. if nil, a name as the first port name is used
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create_port(s, name, options \\ [])

create an input port optional arguments

  • :width, the width. default is 1
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decode(s, condition, choices, options \\ [])

pick one choice out of 2^n choices based on condition value optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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die_when(s, str, options \\ [])

define an assertion. If the given expr evalue to verilog reue value the simulation will die

optional arguments:

  • :flop_by, clock name of the flop if existed

expose the wire as a port. width and direction are automatically figured out

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fsm(s, graph, options \\ [])

define a finite state machine, from a list of: {state, transitions} where state is a atom. transition is a list of: {condition, next_state}

optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop, required
  • :reset_by, an expression of reset condition, optional
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invoke(s, func)

Invoke the func with s. This is used to keep the pipe flowing

s |> invoke(func) is just a fancy way to say func.(s)

The beauty comes in when you have:

s
|> other_function()
|> invoke(fn s ->
   case something do
     0 -> s
     1 -> s |> something_else()
   end
   end)
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roll_in(s, enum, function)

This is Enum.reduce with first 2 argument switched, to keep the pipe flowing

sink one wire or a list of wires, so they have a fake load and not to be auto-exposed

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switch(s, subject, list, options \\ [])

pick one choice out of n choices based on subject matching condition. the list is a list of {condition, choice} tuple optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop